1. Field of the Invention
The present invention relates to a layout pattern generation device for semiconductor integrated circuits and a method used by the layout pattern generation device, and more particularly, it relates to a layout pattern generation device and a method for semiconductor integrated circuits for generating a layout pattern in which transistor sizes in an existing layout pattern are changed.
2. Description of the Related Art
FIGS. 1A and 1B are block diagrams showing conventional computer Aided Design (CAD) systems for generating the layout pattern of a LSI (a large scale integrated circuit).
There is the "LAS" that is a product of CADENCE company as one of examples of the conventional CAD systems. This CAD system "LAS" comprises the symbolic layout synthetic means 2 and the compaction means 4 and the symbolic polygon conversion means 6, as shown in FIG. 1A.
In the conventional CAD system shown in FIG. 1A, a symbolic layout is synthesized based on the circuit connection information 1 by the symbolic layout synthesis means 2. Then, the symbolic layout 3 is compacted by the compaction means 4, the compacted symbolic layout is converted to polygon data items by the symbolic polygon conversion means 6. Thereby, the layout pattern 7 is generated.
FIG. 1B is a block diagram showing the configuration of another conventional CAD system.
The conventional CAD system shown in FIG. 1B comprises a polygon symbolic conversion means 9, a compaction means 11, and a symbolic polygon conversion means 13. In this CAD system shown in FIG. 1B, a symbolic layout 10 is generated based on an existing layout pattern 8 by the polygon symbolic conversion means 9. Then, the symbolic layout 10 is compacted by the compaction means 11, the compacted symbolic layout is converted to polygon data items by the symbolic polygon conversion means 13. Thereby, the new layout pattern 14 is generated.
FIG. 2 is a block diagram showing a configuration of another conventional CAD system. The CAD system shown in FIG. 2 further comprises means for performing an optimization process for transistor sizes. That is, the CAD system shown in FIG. 2 has the function of the above optimization means in addition to the function of the conventional CAD system shown in FIG. 1B.
The information of the conventional CAD system shown in FIG. 2 is following: S. Kishida, et al., "Transistor Size Optimization in Layout Design Rule Migration", Proceedings of the IEEE 1994 Custom Integrated Circuits Conference, pp. 541-544).
That is, the CAD system shown in FIG. 2 comprises the circuit extraction means 15, the transistor size optimization means 17, and the symbol conversion means 18. In both the CAD systems shown in FIG. 1B and FIG. 2, the processes from the existing layout pattern process to the new layout pattern generation process are same. After these processes, in the CAD system shown in FIG. 2, data items as circuit connection information 16 are extracted from the new layout pattern 14 by the circuit extraction means 15. The transistor sizes are optimized by using the circuit connection information 16 by the transistor size optimization means 17. Then, the sizes of transistors in the compacted symbolic layout 12 are changed according to the result of the optimization process by the symbol conversion means 18. Then, the symbolic layout 19, whose transistor sizes has been changed, is compacted by the compaction means 11. The compacted symbolic layout 12 is converted to polygon data items by the symbolic polygon conversion means 13. Thereby, a new layout pattern 14 is generated.
After the new symbolic layout pattern is obtained, the circuit extraction means 15, and the symbolic polygon conversion means 13 are repeatedly processed.
In the conventional CAD system shown in FIG. 1A, it is possible to change the transistor sizes based on the circuit connection information and to apply the changed transistor sizes to the layout pattern. Thereby, it can be easily performed to change the layout pattern. However, there is a problem that it is impossible to generate a new layout pattern by using any existing layout pattern because this conventional CAD system shown in FIG. 1A generates a new layout pattern only by using the circuit connection information.
In the conventional CAD system shown in FIG. 1B, although it is possible to generate a new layout pattern, in which transistor sizes in an existing layout pattern have been changed, by changing parameters of the transistor symbols in symbolic data items, it must require many times to perform the new layout pattern generation process when the number of data items are large. In this case, if the transistor size changing operation is performed for the circuit connection information and this operation result can be reflected to or used for the layout pattern, the new layout pattern generation process can be executed efficiently. However, it is difficult in configuration and function to execute the above processes by the conventional CAD system.
As described above, it is impossible to change the transistor sizes in the conventional CAD systems without a hand process. That is, it is difficult to optimize the transistor sizes in the layout pattern by using the conventional CAD systems.
On the other hand, the conventional CAD system shown in FIG. 2 includes the function of the transistor size optimization process in addition to the function of the conventional CAD system shown in FIG. 1B. Therefore, the transistor size optimization process can be executed by the CAD system shown in FIG. 2. However, the conventional CAD system shown in FIG. 2 can execute the transistor size optimization process only by using a layout pattern in which the compaction process has already been completed. Therefore it must require many times to execute the transistor size optimization process. In addition to this drawback, there is the drawback that a compaction ratio or a compaction effect based on the changing of the transistor sizes becomes bad after the layout pattern is compacted one time.
When the transistor size changing process is executed by a hand processing in the conventional CAD system, the symbolic data items or the circuit connection information extracted from the layout pattern are used. Accordingly, when the number of data items are large, it becomes impossible to perform the transistor size changing process using the symbolic data items. Furthermore, it is difficult to use the circuit connection information extracted from the layout pattern by a hand processing.